A content addressable memory (CAM) is a storage device in which storage locations are identified by their contents, not by names or positions. A search argument is presented to the CAM and the location that matches the argument asserts a corresponding match line. One use for such a memory is in dynamically translating logical addresses to physical addresses in a virtual memory system. In this case the logical address is the search argument and the physical address is produced as a result of the dynamic match line selecting the physical address from a storage location in a random access memory (RAM).
The major technical challenge in the design of an integrated circuit CAM cell is to achieve the desired function, performance and cost objectives by optimizing the speed, density, power consumption, risk, and design time of the implementation's circuitry.
Three prior art content addressable memory (CAM) cells that are compatible with a dynamic match line design are shown in FIGS. 1A, 1B, and 1C. The first (FIG. 1A) and smallest CAM cell, a 4-transistor design, requires a circuit design that necessitates multiplexing the power, row selection and CAM functions all onto a single row signal (10). This design is considered to be too difficult to meet speed goals as well as being risky.
The second prior art CAM cell (FIG. 1B) has a separate match line (12) and row select (14). It uses a more traditional and conservative design that can be easily sized to meet the speed goals presented above; however, it consumes about three times the chip area of a standard six transistor RAM cell.
The third prior art CAM cell (FIG. 1C) is slower due to the two series P-devices (14, 16) required to charge the match line (18). Although this cell can be very chip-area efficient, the row pitch of the most area efficient version of the cell mismatches the row pitch of a six transistor RAM by more than 50%. The cell also makes the column line drivers pitch extremely narrow. The amount of chip area lost matching the pitch of this cell consumes any chip area savings gained by the cell itself.
The design of a satisfactory CAM cell has to satisfy the following constraints:
1. It needs to be fast: all 48 by 27-bit entries must be searched for a match in about one half of a clock phase (15 ns).
2. It needs to be small and meet the pitch of corresponding RAM cells.
3. It must consume less than 200 mW of power at a 16 Mhz microcycle frequency.
The need for low power and tight layout pitch immediately disallows all static design approaches. A static design requires forty-eight 27-input AND gates to implement the CAM match function. It is of course possible to construct a low-power 27-input AND gate that operates within the 15 ns design goal; however, it requires building three levels of three input NAND and NOR gates and is not amenable to the pitch or area constraints mentioned above. A simple static load approach that does meet pitch and area constraints fails to meet low-power requirements. A static load approach consumes more than five times as much power as a dynamic match-line approach.
It is therefore an object of the present invention to provide a dynamic match line content addressable memory cell that consumes low power and conforms to a tight layout pitch to meet the needs of a corresponding random access memory.